David McCreight,
You configured uPP as a receive mode with FPGA.
Here you have used channel-A in receive mode as per your code.
In this case uPP init gets fail at regular intervel period.
I think so, it's not correct way to reinit uPP at the time of every uPP failure in the real time.
Refer the uPP functional block diagram from OOMAPL138 TRM for receive mode.
From 33.2.1.2 Receive Mode (Single Data Rate) section gives the detail for clock setting.
You will get steps for initializing and running the uPP peripheral in various
modes,under the section "33.2.6 Initialization and Operation".