Hi,
Please refer page no 857 to 865 in Technical referenc manual SPRUH77A www.ti.com/lit/ug/spruh77a/spruh77a.pdf for ASRAM example configuration (Toshiba’s TC55V1664FT-12) and followed by the NAND flash interface requirements and this procedure taking into account for PCB delays also the tricky thing is you need to study and implement the same in FPGA with a bit modification in timing parameter.
Note:
You need to consider both AC timing requirements of the ASRAM or FPGA as well as the AC timing requirements of the EMIFA (OMAP-L138). These can be found in the data sheet for each respective device. The read and write asynchronous cycles are programmed separately in the Asynchronous configuration registers (CEnCFG).
Regards
Antony
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