Forum Post: RE: Setup and hold time of the emif (omap l138b)

Hi Reshma,

In addition to the above response, i hope, it would be useful for you to understand the A54SX08A Timing Characteristics of Actel SX-A Family FPGA Datasheet as below:

http://www.actel.com/documents/SXA_DS.pdf

Please find the details of Asynchronous Hold Time (t_HASYN), Flip-Flop Data Input Set-Up time (t_SUD) & Flip-Flop Data Input Hold(t_HD) in Table 2-14 of A54SX08A Timing Characteristics in page no. 38 of the datasheet link above.

As Antony suggested in the above mail thread, you need to considier both the AC timing requirements of  Asynchronous SRAM/DRAM device & FPGA as well as the AC timing requirements of the EMIFA (OMAP-L138).

Thanks & regards,

Sivaraj K